first
This commit is contained in:
@ -0,0 +1,251 @@
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;********************************************************************************
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||||
;* File Name : startup_stm32wl54xx_cm0plus.s
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;* Author : MCD Application Team
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||||
;* Description : STM32WL54xx devices vector table for MDK-ARM toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == Reset_Handler
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;* - Set the vector table entries with the exceptions ISR address
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;* - Branches to __main in the C library (which eventually
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;* calls main()).
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;* After Reset the Cortex-M0+ processor is in Thread mode,
|
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;* priority is Privileged, and the Stack is set to Main.
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||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;********************************************************************************
|
||||
;* @attention
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;*
|
||||
;* Copyright (c) 2020-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
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||||
;********************************************************************************
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||||
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; Amount of memory (in bytes) allocated for Stack
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; Tailor this value to your application needs
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000200
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD TZIC_ILA_IRQHandler ; Security Interrupt controller illegal access Interrupts
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DCD PVD_PVM_IRQHandler ; PVD and PVM detector
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DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) + SSR Underflow and LSECSS Interrupts
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DCD RCC_FLASH_C1SEV_IRQHandler ; RCC1 and FLASH and CPU1 M4 SEV Interrupts
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DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupts
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DCD EXTI3_2_IRQHandler ; XTI Line 3:2 Interrupts
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DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupts
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DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupts
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DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupts
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DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4, 5, 6, 7 Interrupts
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DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
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DCD LPTIM1_IRQHandler ; LPTIM1 global Interrupt
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DCD LPTIM2_IRQHandler ; LPTIM2 global Interrupt
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DCD LPTIM3_IRQHandler ; LPTIM3 global Interrupt
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DCD TIM1_IRQHandler ; TIM1 Interrupt
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DCD TIM2_IRQHandler ; TIM2 Interrupt
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DCD TIM16_IRQHandler ; TIM16 Interrupt
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DCD TIM17_IRQHandler ; TIM17 Interrupt
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DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupts
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DCD HSEM_IRQHandler ; Semaphore Interrupt
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DCD RNG_IRQHandler ; RNG Interrupt
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DCD AES_PKA_IRQHandler ; AES and PKA Interrupts
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DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
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DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
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DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
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DCD SPI1_IRQHandler ; SPI1 Interrupts
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DCD SPI2_IRQHandler ; SPI2 Interrupt
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DCD USART1_IRQHandler ; USART1 Interrupt
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DCD USART2_IRQHandler ; USART2 Interrupt
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DCD LPUART1_IRQHandler ; LPUART1 Interrupt
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DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
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DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT TZIC_ILA_IRQHandler [WEAK]
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EXPORT PVD_PVM_IRQHandler [WEAK]
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EXPORT RTC_LSECSS_IRQHandler [WEAK]
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EXPORT RCC_FLASH_C1SEV_IRQHandler [WEAK]
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EXPORT EXTI1_0_IRQHandler [WEAK]
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EXPORT EXTI3_2_IRQHandler [WEAK]
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EXPORT EXTI15_4_IRQHandler [WEAK]
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EXPORT ADC_COMP_DAC_IRQHandler [WEAK]
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EXPORT DMA1_Channel1_2_3_IRQHandler [WEAK]
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EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
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EXPORT DMA2_DMAMUX1_OVR_IRQHandler [WEAK]
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EXPORT LPTIM1_IRQHandler [WEAK]
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EXPORT LPTIM2_IRQHandler [WEAK]
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EXPORT LPTIM3_IRQHandler [WEAK]
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EXPORT TIM1_IRQHandler [WEAK]
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EXPORT TIM2_IRQHandler [WEAK]
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EXPORT TIM16_IRQHandler [WEAK]
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EXPORT TIM17_IRQHandler [WEAK]
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EXPORT IPCC_C2_RX_C2_TX_IRQHandler [WEAK]
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EXPORT HSEM_IRQHandler [WEAK]
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EXPORT RNG_IRQHandler [WEAK]
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EXPORT AES_PKA_IRQHandler [WEAK]
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EXPORT I2C1_IRQHandler [WEAK]
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EXPORT I2C2_IRQHandler [WEAK]
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EXPORT I2C3_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT SPI2_IRQHandler [WEAK]
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EXPORT USART1_IRQHandler [WEAK]
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EXPORT USART2_IRQHandler [WEAK]
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EXPORT LPUART1_IRQHandler [WEAK]
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EXPORT SUBGHZSPI_IRQHandler [WEAK]
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EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
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TZIC_ILA_IRQHandler
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PVD_PVM_IRQHandler
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RTC_LSECSS_IRQHandler
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RCC_FLASH_C1SEV_IRQHandler
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EXTI1_0_IRQHandler
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EXTI3_2_IRQHandler
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EXTI15_4_IRQHandler
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ADC_COMP_DAC_IRQHandler
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DMA1_Channel1_2_3_IRQHandler
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DMA1_Channel4_5_6_7_IRQHandler
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||||
DMA2_DMAMUX1_OVR_IRQHandler
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LPTIM1_IRQHandler
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LPTIM2_IRQHandler
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LPTIM3_IRQHandler
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||||
TIM1_IRQHandler
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||||
TIM2_IRQHandler
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||||
TIM16_IRQHandler
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||||
TIM17_IRQHandler
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||||
IPCC_C2_RX_C2_TX_IRQHandler
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HSEM_IRQHandler
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RNG_IRQHandler
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AES_PKA_IRQHandler
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I2C1_IRQHandler
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I2C2_IRQHandler
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I2C3_IRQHandler
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SPI1_IRQHandler
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SPI2_IRQHandler
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USART1_IRQHandler
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USART2_IRQHandler
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LPUART1_IRQHandler
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SUBGHZSPI_IRQHandler
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SUBGHZ_Radio_IRQHandler
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B .
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ENDP
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ALIGN
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;********************************************************************************
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; User Stack and Heap initialization
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;********************************************************************************
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ALIGN
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ENDIF
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END
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@ -0,0 +1,363 @@
|
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;********************************************************************************
|
||||
;* File Name : startup_stm32wl54xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32WL54xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;********************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2020-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;********************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
||||
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC_IRQHandler ; ADC Interrupt
|
||||
DCD DAC_IRQHandler ; DAC Interrupt
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
|
||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
|
||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
||||
DCD AES_IRQHandler ; AES Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT DAC_IRQHandler [WEAK]
|
||||
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
|
||||
EXPORT COMP_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM17_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
||||
EXPORT SUBGHZSPI_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
|
||||
EXPORT HSEM_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
|
||||
EXPORT AES_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT PKA_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel7_IRQHandler [WEAK]
|
||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_PVM_IRQHandler
|
||||
TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC_IRQHandler
|
||||
DAC_IRQHandler
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
COMP_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_IRQHandler
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM16_IRQHandler
|
||||
TIM17_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
LPTIM3_IRQHandler
|
||||
SUBGHZSPI_IRQHandler
|
||||
IPCC_C1_RX_IRQHandler
|
||||
IPCC_C1_TX_IRQHandler
|
||||
HSEM_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
SUBGHZ_Radio_IRQHandler
|
||||
AES_IRQHandler
|
||||
RNG_IRQHandler
|
||||
PKA_IRQHandler
|
||||
DMA2_Channel1_IRQHandler
|
||||
DMA2_Channel2_IRQHandler
|
||||
DMA2_Channel3_IRQHandler
|
||||
DMA2_Channel4_IRQHandler
|
||||
DMA2_Channel5_IRQHandler
|
||||
DMA2_Channel6_IRQHandler
|
||||
DMA2_Channel7_IRQHandler
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;********************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;********************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@ -0,0 +1,251 @@
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32wl55xx_cm0plus.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M0+ processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;********************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2020-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;********************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD TZIC_ILA_IRQHandler ; Security Interrupt controller illegal access Interrupts
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
||||
DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) + SSR Underflow and LSECSS Interrupts
|
||||
DCD RCC_FLASH_C1SEV_IRQHandler ; RCC1 and FLASH and CPU1 M4 SEV Interrupts
|
||||
DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupts
|
||||
DCD EXTI3_2_IRQHandler ; XTI Line 3:2 Interrupts
|
||||
DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupts
|
||||
DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupts
|
||||
DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupts
|
||||
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4, 5, 6, 7 Interrupts
|
||||
DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 global Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 global Interrupt
|
||||
DCD LPTIM3_IRQHandler ; LPTIM3 global Interrupt
|
||||
DCD TIM1_IRQHandler ; TIM1 Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Interrupt
|
||||
DCD TIM16_IRQHandler ; TIM16 Interrupt
|
||||
DCD TIM17_IRQHandler ; TIM17 Interrupt
|
||||
DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupts
|
||||
DCD HSEM_IRQHandler ; Semaphore Interrupt
|
||||
DCD RNG_IRQHandler ; RNG Interrupt
|
||||
DCD AES_PKA_IRQHandler ; AES and PKA Interrupts
|
||||
DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
|
||||
DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
|
||||
DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupts
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT TZIC_ILA_IRQHandler [WEAK]
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT RTC_LSECSS_IRQHandler [WEAK]
|
||||
EXPORT RCC_FLASH_C1SEV_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_0_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_2_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_4_IRQHandler [WEAK]
|
||||
EXPORT ADC_COMP_DAC_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_2_3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
|
||||
EXPORT DMA2_DMAMUX1_OVR_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM1_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM17_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C2_RX_C2_TX_IRQHandler [WEAK]
|
||||
EXPORT HSEM_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT AES_PKA_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT I2C2_IRQHandler [WEAK]
|
||||
EXPORT I2C3_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT SUBGHZSPI_IRQHandler [WEAK]
|
||||
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
|
||||
|
||||
TZIC_ILA_IRQHandler
|
||||
PVD_PVM_IRQHandler
|
||||
RTC_LSECSS_IRQHandler
|
||||
RCC_FLASH_C1SEV_IRQHandler
|
||||
EXTI1_0_IRQHandler
|
||||
EXTI3_2_IRQHandler
|
||||
EXTI15_4_IRQHandler
|
||||
ADC_COMP_DAC_IRQHandler
|
||||
DMA1_Channel1_2_3_IRQHandler
|
||||
DMA1_Channel4_5_6_7_IRQHandler
|
||||
DMA2_DMAMUX1_OVR_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
LPTIM3_IRQHandler
|
||||
TIM1_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM16_IRQHandler
|
||||
TIM17_IRQHandler
|
||||
IPCC_C2_RX_C2_TX_IRQHandler
|
||||
HSEM_IRQHandler
|
||||
RNG_IRQHandler
|
||||
AES_PKA_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
I2C2_IRQHandler
|
||||
I2C3_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
SUBGHZSPI_IRQHandler
|
||||
SUBGHZ_Radio_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;********************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;********************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@ -0,0 +1,363 @@
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32wl55xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;********************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2020-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;********************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
||||
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC_IRQHandler ; ADC Interrupt
|
||||
DCD DAC_IRQHandler ; DAC Interrupt
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
|
||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
|
||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
||||
DCD AES_IRQHandler ; AES Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT DAC_IRQHandler [WEAK]
|
||||
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
|
||||
EXPORT COMP_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM17_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
||||
EXPORT SUBGHZSPI_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
|
||||
EXPORT HSEM_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
|
||||
EXPORT AES_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT PKA_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel7_IRQHandler [WEAK]
|
||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_PVM_IRQHandler
|
||||
TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC_IRQHandler
|
||||
DAC_IRQHandler
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
COMP_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_IRQHandler
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM16_IRQHandler
|
||||
TIM17_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
LPTIM3_IRQHandler
|
||||
SUBGHZSPI_IRQHandler
|
||||
IPCC_C1_RX_IRQHandler
|
||||
IPCC_C1_TX_IRQHandler
|
||||
HSEM_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
SUBGHZ_Radio_IRQHandler
|
||||
AES_IRQHandler
|
||||
RNG_IRQHandler
|
||||
PKA_IRQHandler
|
||||
DMA2_Channel1_IRQHandler
|
||||
DMA2_Channel2_IRQHandler
|
||||
DMA2_Channel3_IRQHandler
|
||||
DMA2_Channel4_IRQHandler
|
||||
DMA2_Channel5_IRQHandler
|
||||
DMA2_Channel6_IRQHandler
|
||||
DMA2_Channel7_IRQHandler
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;********************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;********************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@ -0,0 +1,357 @@
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32wle4xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32WLE4xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;********************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2020-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;********************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
||||
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC_IRQHandler ; ADC Interrupt
|
||||
DCD DAC_IRQHandler ; DAC Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
|
||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
||||
DCD AES_IRQHandler ; AES Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT DAC_IRQHandler [WEAK]
|
||||
EXPORT COMP_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM17_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
||||
EXPORT SUBGHZSPI_IRQHandler [WEAK]
|
||||
EXPORT HSEM_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
|
||||
EXPORT AES_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT PKA_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel7_IRQHandler [WEAK]
|
||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_PVM_IRQHandler
|
||||
TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC_IRQHandler
|
||||
DAC_IRQHandler
|
||||
COMP_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_IRQHandler
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM16_IRQHandler
|
||||
TIM17_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
LPTIM3_IRQHandler
|
||||
SUBGHZSPI_IRQHandler
|
||||
HSEM_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
SUBGHZ_Radio_IRQHandler
|
||||
AES_IRQHandler
|
||||
RNG_IRQHandler
|
||||
PKA_IRQHandler
|
||||
DMA2_Channel1_IRQHandler
|
||||
DMA2_Channel2_IRQHandler
|
||||
DMA2_Channel3_IRQHandler
|
||||
DMA2_Channel4_IRQHandler
|
||||
DMA2_Channel5_IRQHandler
|
||||
DMA2_Channel6_IRQHandler
|
||||
DMA2_Channel7_IRQHandler
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;********************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;********************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@ -0,0 +1,357 @@
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32wle5xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32WLE5xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;********************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2020-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;********************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
||||
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC_IRQHandler ; ADC Interrupt
|
||||
DCD DAC_IRQHandler ; DAC Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupts
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD LPTIM3_IRQHandler ; LPTIM3 Interrupt
|
||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
||||
DCD AES_IRQHandler ; AES Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT DAC_IRQHandler [WEAK]
|
||||
EXPORT COMP_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM17_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT LPTIM3_IRQHandler [WEAK]
|
||||
EXPORT SUBGHZSPI_IRQHandler [WEAK]
|
||||
EXPORT HSEM_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
|
||||
EXPORT AES_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT PKA_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel7_IRQHandler [WEAK]
|
||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_PVM_IRQHandler
|
||||
TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC_IRQHandler
|
||||
DAC_IRQHandler
|
||||
COMP_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_IRQHandler
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM16_IRQHandler
|
||||
TIM17_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
LPTIM3_IRQHandler
|
||||
SUBGHZSPI_IRQHandler
|
||||
HSEM_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
SUBGHZ_Radio_IRQHandler
|
||||
AES_IRQHandler
|
||||
RNG_IRQHandler
|
||||
PKA_IRQHandler
|
||||
DMA2_Channel1_IRQHandler
|
||||
DMA2_Channel2_IRQHandler
|
||||
DMA2_Channel3_IRQHandler
|
||||
DMA2_Channel4_IRQHandler
|
||||
DMA2_Channel5_IRQHandler
|
||||
DMA2_Channel6_IRQHandler
|
||||
DMA2_Channel7_IRQHandler
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;********************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;********************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@ -0,0 +1,301 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32wl54xx_cm0plus.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32WL54xx devices Cortex-M0+ vector table for GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address,
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M0+ processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2020-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m0plus
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
ldr r2, =_sidata
|
||||
movs r3, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
movs r3, #0
|
||||
b LoopFillZerobss
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* The STM32WL54xx Cortex-M0+ vector table. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word TZIC_ILA_IRQHandler /* TZIC ILA Interrupt */
|
||||
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
|
||||
.word RTC_LSECSS_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
|
||||
.word RCC_FLASH_C1SEV_IRQHandler /* RCC and FLASH and CPU1 M4 SEV Interrupt */
|
||||
.word EXTI1_0_IRQHandler /* EXTI Line 1:0 Interrupt */
|
||||
.word EXTI3_2_IRQHandler /* EXTI Line 3:2 Interrupt */
|
||||
.word EXTI15_4_IRQHandler /* EXTI Line 15:4 interrupt */
|
||||
.word ADC_COMP_DAC_IRQHandler /* ADC, COMP1, COMP2, DAC Interrupt */
|
||||
.word DMA1_Channel1_2_3_IRQHandler /* DMA1 Channel 1 to 3 Interrupt */
|
||||
.word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channels 4,5,6,7 Interrupt */
|
||||
.word DMA2_DMAMUX1_OVR_IRQHandler /* DMA2 Channels[1..7] and DMAMUX Overrun Interrupts */
|
||||
.word LPTIM1_IRQHandler /* LPTIM1 Global Interrupt */
|
||||
.word LPTIM2_IRQHandler /* LPTIM2 Global Interrupt */
|
||||
.word LPTIM3_IRQHandler /* LPTIM3 Global Interrupt */
|
||||
.word TIM1_IRQHandler /* TIM1 Global Interrupt */
|
||||
.word TIM2_IRQHandler /* TIM2 Global Interrupt */
|
||||
.word TIM16_IRQHandler /* TIM16 Global Interrupt */
|
||||
.word TIM17_IRQHandler /* TIM17 Global Interrupt */
|
||||
.word IPCC_C2_RX_C2_TX_IRQHandler /* IPCC RX Occupied and TX Free Interrupt Interrupt */
|
||||
.word HSEM_IRQHandler /* Semaphore Interrupt */
|
||||
.word RNG_IRQHandler /* RNG Interrupt */
|
||||
.word AES_PKA_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
|
||||
.word I2C1_IRQHandler /* I2C1 Event and Error Interrupt */
|
||||
.word I2C2_IRQHandler /* I2C2 Event and Error Interrupt */
|
||||
.word I2C3_IRQHandler /* I2C3 Event and Error Interrupt */
|
||||
.word SPI1_IRQHandler /* SPI1 Interrupt */
|
||||
.word SPI2_IRQHandler /* SPI2 Interrupt */
|
||||
.word USART1_IRQHandler /* USART1 Interrupt */
|
||||
.word USART2_IRQHandler /* USART2 Interrupt */
|
||||
.word LPUART1_IRQHandler /* LPUART1 Interrupt */
|
||||
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI Interrupt */
|
||||
.word SUBGHZ_Radio_IRQHandler /* SUBGHZ Radio Interrupt */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak TZIC_ILA_IRQHandler
|
||||
.thumb_set TZIC_ILA_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_LSECSS_IRQHandler
|
||||
.thumb_set RTC_LSECSS_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_FLASH_C1SEV_IRQHandler
|
||||
.thumb_set RCC_FLASH_C1SEV_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_0_IRQHandler
|
||||
.thumb_set EXTI1_0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_2_IRQHandler
|
||||
.thumb_set EXTI3_2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_4_IRQHandler
|
||||
.thumb_set EXTI15_4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_COMP_DAC_IRQHandler
|
||||
.thumb_set ADC_COMP_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_2_3_IRQHandler
|
||||
.thumb_set DMA1_Channel1_2_3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_5_6_7_IRQHandler
|
||||
.thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMA2_DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_IRQHandler
|
||||
.thumb_set TIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C2_RX_C2_TX_IRQHandler
|
||||
.thumb_set IPCC_C2_RX_C2_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM_IRQHandler
|
||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES_PKA_IRQHandler
|
||||
.thumb_set AES_PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_IRQHandler
|
||||
.thumb_set I2C1_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_IRQHandler
|
||||
.thumb_set I2C2_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_IRQHandler
|
||||
.thumb_set I2C3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SUBGHZSPI_IRQHandler
|
||||
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak SUBGHZ_Radio_IRQHandler
|
||||
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
|
||||
|
||||
.weak SystemInit
|
||||
@ -0,0 +1,433 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32wl54xx_cm4.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32WL54xx devices Cortex-M4 vector table for GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address,
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2020-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
ldr r2, =_sidata
|
||||
movs r3, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
movs r3, #0
|
||||
b LoopFillZerobss
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* The STM32WL54xx Cortex-M4 vector table. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler /* Window Watchdog interrupt */
|
||||
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
|
||||
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
|
||||
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
|
||||
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
|
||||
.word RCC_IRQHandler /* RCC global interrupt */
|
||||
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
|
||||
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
|
||||
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
|
||||
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
|
||||
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
|
||||
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
|
||||
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
|
||||
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
|
||||
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
|
||||
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
|
||||
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
|
||||
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
|
||||
.word ADC_IRQHandler /* ADC interrupt */
|
||||
.word DAC_IRQHandler /* DAC interrupt */
|
||||
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
|
||||
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
|
||||
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
|
||||
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
|
||||
.word TIM1_UP_IRQHandler /* Timer 1 Update */
|
||||
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
|
||||
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
|
||||
.word TIM2_IRQHandler /* TIM2 global interrupt */
|
||||
.word TIM16_IRQHandler /* Timer 16 global interrupt */
|
||||
.word TIM17_IRQHandler /* Timer 17 global interrupt */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
|
||||
.word SPI1_IRQHandler /* SPI1 global interrupt */
|
||||
.word SPI2_IRQHandler /* SPI2 global interrupt */
|
||||
.word USART1_IRQHandler /* USART1 global interrupt */
|
||||
.word USART2_IRQHandler /* USART2 global interrupt */
|
||||
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
|
||||
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
|
||||
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
|
||||
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
|
||||
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
|
||||
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
|
||||
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
|
||||
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
|
||||
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
|
||||
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
|
||||
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
|
||||
.word AES_IRQHandler /* AES global interrupt */
|
||||
.word RNG_IRQHandler /* RNG interrupt */
|
||||
.word PKA_IRQHandler /* PKA interrupt */
|
||||
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
|
||||
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
|
||||
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
|
||||
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
|
||||
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
|
||||
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
|
||||
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
|
||||
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DAC_IRQHandler
|
||||
.thumb_set DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak C2SEV_PWR_C2H_IRQHandler
|
||||
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMP_IRQHandler
|
||||
.thumb_set COMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SUBGHZSPI_IRQHandler
|
||||
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_RX_IRQHandler
|
||||
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_TX_IRQHandler
|
||||
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM_IRQHandler
|
||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SUBGHZ_Radio_IRQHandler
|
||||
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES_IRQHandler
|
||||
.thumb_set AES_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PKA_IRQHandler
|
||||
.thumb_set PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel1_IRQHandler
|
||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel2_IRQHandler
|
||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel3_IRQHandler
|
||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel4_IRQHandler
|
||||
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel5_IRQHandler
|
||||
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel6_IRQHandler
|
||||
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel7_IRQHandler
|
||||
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
.weak SystemInit
|
||||
@ -0,0 +1,301 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32wl55xx_cm0plus.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32WL55xx devices Cortex-M0+ vector table for GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address,
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M0+ processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2020-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m0plus
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
ldr r2, =_sidata
|
||||
movs r3, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
movs r3, #0
|
||||
b LoopFillZerobss
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* The STM32WL55xx Cortex-M0+ vector table. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word TZIC_ILA_IRQHandler /* TZIC ILA Interrupt */
|
||||
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
|
||||
.word RTC_LSECSS_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
|
||||
.word RCC_FLASH_C1SEV_IRQHandler /* RCC and FLASH and CPU1 M4 SEV Interrupt */
|
||||
.word EXTI1_0_IRQHandler /* EXTI Line 1:0 Interrupt */
|
||||
.word EXTI3_2_IRQHandler /* EXTI Line 3:2 Interrupt */
|
||||
.word EXTI15_4_IRQHandler /* EXTI Line 15:4 interrupt */
|
||||
.word ADC_COMP_DAC_IRQHandler /* ADC, COMP1, COMP2, DAC Interrupt */
|
||||
.word DMA1_Channel1_2_3_IRQHandler /* DMA1 Channel 1 to 3 Interrupt */
|
||||
.word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channels 4,5,6,7 Interrupt */
|
||||
.word DMA2_DMAMUX1_OVR_IRQHandler /* DMA2 Channels[1..7] and DMAMUX Overrun Interrupts */
|
||||
.word LPTIM1_IRQHandler /* LPTIM1 Global Interrupt */
|
||||
.word LPTIM2_IRQHandler /* LPTIM2 Global Interrupt */
|
||||
.word LPTIM3_IRQHandler /* LPTIM3 Global Interrupt */
|
||||
.word TIM1_IRQHandler /* TIM1 Global Interrupt */
|
||||
.word TIM2_IRQHandler /* TIM2 Global Interrupt */
|
||||
.word TIM16_IRQHandler /* TIM16 Global Interrupt */
|
||||
.word TIM17_IRQHandler /* TIM17 Global Interrupt */
|
||||
.word IPCC_C2_RX_C2_TX_IRQHandler /* IPCC RX Occupied and TX Free Interrupt Interrupt */
|
||||
.word HSEM_IRQHandler /* Semaphore Interrupt */
|
||||
.word RNG_IRQHandler /* RNG Interrupt */
|
||||
.word AES_PKA_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
|
||||
.word I2C1_IRQHandler /* I2C1 Event and Error Interrupt */
|
||||
.word I2C2_IRQHandler /* I2C2 Event and Error Interrupt */
|
||||
.word I2C3_IRQHandler /* I2C3 Event and Error Interrupt */
|
||||
.word SPI1_IRQHandler /* SPI1 Interrupt */
|
||||
.word SPI2_IRQHandler /* SPI2 Interrupt */
|
||||
.word USART1_IRQHandler /* USART1 Interrupt */
|
||||
.word USART2_IRQHandler /* USART2 Interrupt */
|
||||
.word LPUART1_IRQHandler /* LPUART1 Interrupt */
|
||||
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI Interrupt */
|
||||
.word SUBGHZ_Radio_IRQHandler /* SUBGHZ Radio Interrupt */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak TZIC_ILA_IRQHandler
|
||||
.thumb_set TZIC_ILA_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_LSECSS_IRQHandler
|
||||
.thumb_set RTC_LSECSS_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_FLASH_C1SEV_IRQHandler
|
||||
.thumb_set RCC_FLASH_C1SEV_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_0_IRQHandler
|
||||
.thumb_set EXTI1_0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_2_IRQHandler
|
||||
.thumb_set EXTI3_2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_4_IRQHandler
|
||||
.thumb_set EXTI15_4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_COMP_DAC_IRQHandler
|
||||
.thumb_set ADC_COMP_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_2_3_IRQHandler
|
||||
.thumb_set DMA1_Channel1_2_3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_5_6_7_IRQHandler
|
||||
.thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMA2_DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_IRQHandler
|
||||
.thumb_set TIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C2_RX_C2_TX_IRQHandler
|
||||
.thumb_set IPCC_C2_RX_C2_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM_IRQHandler
|
||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES_PKA_IRQHandler
|
||||
.thumb_set AES_PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_IRQHandler
|
||||
.thumb_set I2C1_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_IRQHandler
|
||||
.thumb_set I2C2_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_IRQHandler
|
||||
.thumb_set I2C3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SUBGHZSPI_IRQHandler
|
||||
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak SUBGHZ_Radio_IRQHandler
|
||||
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
|
||||
|
||||
.weak SystemInit
|
||||
@ -0,0 +1,433 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32wl55xx_cm4.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address,
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2020-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
ldr r2, =_sidata
|
||||
movs r3, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
movs r3, #0
|
||||
b LoopFillZerobss
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler /* Window Watchdog interrupt */
|
||||
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
|
||||
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
|
||||
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
|
||||
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
|
||||
.word RCC_IRQHandler /* RCC global interrupt */
|
||||
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
|
||||
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
|
||||
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
|
||||
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
|
||||
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
|
||||
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
|
||||
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
|
||||
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
|
||||
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
|
||||
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
|
||||
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
|
||||
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
|
||||
.word ADC_IRQHandler /* ADC interrupt */
|
||||
.word DAC_IRQHandler /* DAC interrupt */
|
||||
.word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
|
||||
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
|
||||
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
|
||||
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
|
||||
.word TIM1_UP_IRQHandler /* Timer 1 Update */
|
||||
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
|
||||
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
|
||||
.word TIM2_IRQHandler /* TIM2 global interrupt */
|
||||
.word TIM16_IRQHandler /* Timer 16 global interrupt */
|
||||
.word TIM17_IRQHandler /* Timer 17 global interrupt */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
|
||||
.word SPI1_IRQHandler /* SPI1 global interrupt */
|
||||
.word SPI2_IRQHandler /* SPI2 global interrupt */
|
||||
.word USART1_IRQHandler /* USART1 global interrupt */
|
||||
.word USART2_IRQHandler /* USART2 global interrupt */
|
||||
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
|
||||
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
|
||||
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
|
||||
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
|
||||
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
|
||||
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
|
||||
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
|
||||
.word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
|
||||
.word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
|
||||
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
|
||||
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
|
||||
.word AES_IRQHandler /* AES global interrupt */
|
||||
.word RNG_IRQHandler /* RNG interrupt */
|
||||
.word PKA_IRQHandler /* PKA interrupt */
|
||||
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
|
||||
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
|
||||
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
|
||||
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
|
||||
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
|
||||
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
|
||||
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
|
||||
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DAC_IRQHandler
|
||||
.thumb_set DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak C2SEV_PWR_C2H_IRQHandler
|
||||
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMP_IRQHandler
|
||||
.thumb_set COMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SUBGHZSPI_IRQHandler
|
||||
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_RX_IRQHandler
|
||||
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_TX_IRQHandler
|
||||
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM_IRQHandler
|
||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SUBGHZ_Radio_IRQHandler
|
||||
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES_IRQHandler
|
||||
.thumb_set AES_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PKA_IRQHandler
|
||||
.thumb_set PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel1_IRQHandler
|
||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel2_IRQHandler
|
||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel3_IRQHandler
|
||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel4_IRQHandler
|
||||
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel5_IRQHandler
|
||||
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel6_IRQHandler
|
||||
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel7_IRQHandler
|
||||
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
.weak SystemInit
|
||||
@ -0,0 +1,424 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32wle4xx.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32WLE4xx devices vector table for GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address,
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2020-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
ldr r2, =_sidata
|
||||
movs r3, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
movs r3, #0
|
||||
b LoopFillZerobss
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* The STM32WLE4xx vector table. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler /* Window Watchdog interrupt */
|
||||
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
|
||||
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
|
||||
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
|
||||
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
|
||||
.word RCC_IRQHandler /* RCC global interrupt */
|
||||
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
|
||||
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
|
||||
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
|
||||
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
|
||||
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
|
||||
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
|
||||
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
|
||||
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
|
||||
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
|
||||
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
|
||||
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
|
||||
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
|
||||
.word ADC_IRQHandler /* ADC interrupt */
|
||||
.word DAC_IRQHandler /* DAC interrupt */
|
||||
.word 0 /* Reserved */
|
||||
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
|
||||
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
|
||||
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
|
||||
.word TIM1_UP_IRQHandler /* Timer 1 Update */
|
||||
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
|
||||
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
|
||||
.word TIM2_IRQHandler /* TIM2 global interrupt */
|
||||
.word TIM16_IRQHandler /* Timer 16 global interrupt */
|
||||
.word TIM17_IRQHandler /* Timer 17 global interrupt */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
|
||||
.word SPI1_IRQHandler /* SPI1 global interrupt */
|
||||
.word SPI2_IRQHandler /* SPI2 global interrupt */
|
||||
.word USART1_IRQHandler /* USART1 global interrupt */
|
||||
.word USART2_IRQHandler /* USART2 global interrupt */
|
||||
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
|
||||
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
|
||||
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
|
||||
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
|
||||
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
|
||||
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
|
||||
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
|
||||
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
|
||||
.word AES_IRQHandler /* AES global interrupt */
|
||||
.word RNG_IRQHandler /* RNG interrupt */
|
||||
.word PKA_IRQHandler /* PKA interrupt */
|
||||
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
|
||||
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
|
||||
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
|
||||
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
|
||||
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
|
||||
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
|
||||
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
|
||||
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DAC_IRQHandler
|
||||
.thumb_set DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMP_IRQHandler
|
||||
.thumb_set COMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SUBGHZSPI_IRQHandler
|
||||
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM_IRQHandler
|
||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SUBGHZ_Radio_IRQHandler
|
||||
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES_IRQHandler
|
||||
.thumb_set AES_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PKA_IRQHandler
|
||||
.thumb_set PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel1_IRQHandler
|
||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel2_IRQHandler
|
||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel3_IRQHandler
|
||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel4_IRQHandler
|
||||
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel5_IRQHandler
|
||||
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel6_IRQHandler
|
||||
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel7_IRQHandler
|
||||
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
.weak SystemInit
|
||||
@ -0,0 +1,424 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32wle5xx.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32WLE5xx devices vector table for GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address,
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2020-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
ldr r2, =_sidata
|
||||
movs r3, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
movs r3, #0
|
||||
b LoopFillZerobss
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* The STM32WLE5xx vector table. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler /* Window Watchdog interrupt */
|
||||
.word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
|
||||
.word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
|
||||
.word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
|
||||
.word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
|
||||
.word RCC_IRQHandler /* RCC global interrupt */
|
||||
.word EXTI0_IRQHandler /* EXTI line 0 interrupt */
|
||||
.word EXTI1_IRQHandler /* EXTI line 1 interrupt */
|
||||
.word EXTI2_IRQHandler /* EXTI line 2 interrupt */
|
||||
.word EXTI3_IRQHandler /* EXTI line 3 interrupt */
|
||||
.word EXTI4_IRQHandler /* EXTI line 4 interrupt */
|
||||
.word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
|
||||
.word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
|
||||
.word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
|
||||
.word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
|
||||
.word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
|
||||
.word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
|
||||
.word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
|
||||
.word ADC_IRQHandler /* ADC interrupt */
|
||||
.word DAC_IRQHandler /* DAC interrupt */
|
||||
.word 0 /* Reserved */
|
||||
.word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
|
||||
.word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
|
||||
.word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
|
||||
.word TIM1_UP_IRQHandler /* Timer 1 Update */
|
||||
.word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
|
||||
.word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
|
||||
.word TIM2_IRQHandler /* TIM2 global interrupt */
|
||||
.word TIM16_IRQHandler /* Timer 16 global interrupt */
|
||||
.word TIM17_IRQHandler /* Timer 17 global interrupt */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 event interrupt */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 error interrupt */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
|
||||
.word SPI1_IRQHandler /* SPI1 global interrupt */
|
||||
.word SPI2_IRQHandler /* SPI2 global interrupt */
|
||||
.word USART1_IRQHandler /* USART1 global interrupt */
|
||||
.word USART2_IRQHandler /* USART2 global interrupt */
|
||||
.word LPUART1_IRQHandler /* LPUART1 global interrupt */
|
||||
.word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
|
||||
.word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
|
||||
.word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
|
||||
.word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
|
||||
.word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
|
||||
.word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
|
||||
.word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
|
||||
.word AES_IRQHandler /* AES global interrupt */
|
||||
.word RNG_IRQHandler /* RNG interrupt */
|
||||
.word PKA_IRQHandler /* PKA interrupt */
|
||||
.word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
|
||||
.word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
|
||||
.word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
|
||||
.word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
|
||||
.word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
|
||||
.word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
|
||||
.word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
|
||||
.word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DAC_IRQHandler
|
||||
.thumb_set DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMP_IRQHandler
|
||||
.thumb_set COMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SUBGHZSPI_IRQHandler
|
||||
.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM_IRQHandler
|
||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SUBGHZ_Radio_IRQHandler
|
||||
.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES_IRQHandler
|
||||
.thumb_set AES_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PKA_IRQHandler
|
||||
.thumb_set PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel1_IRQHandler
|
||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel2_IRQHandler
|
||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel3_IRQHandler
|
||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel4_IRQHandler
|
||||
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel5_IRQHandler
|
||||
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel6_IRQHandler
|
||||
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel7_IRQHandler
|
||||
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
.weak SystemInit
|
||||
@ -0,0 +1,40 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08020000;
|
||||
|
||||
/*-Memory Regions-*/
|
||||
/***** FLASH part dedicated to M0+ *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08020000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
|
||||
/***** Non-backup SRAM1 dedicated to M0+ *****/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20004000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
||||
/***** Backup SRAM2 dedicated to M0+ *****/
|
||||
define symbol __ICFEDIT_region_RAM2_start__ = 0x2000C000;
|
||||
define symbol __ICFEDIT_region_RAM2_end__ = 0x2000FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
place in RAM2_region { };
|
||||
@ -0,0 +1,40 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
|
||||
/*-Memory Regions-*/
|
||||
/***** FLASH part dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
|
||||
/***** Non-backup SRAM1 dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
|
||||
/***** Backup SRAM2 dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_RAM2_start__ = 0x20008000;
|
||||
define symbol __ICFEDIT_region_RAM2_end__ = 0x2000BFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
place in RAM2_region { };
|
||||
@ -0,0 +1,35 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x2000C000;
|
||||
|
||||
/*-Memory Regions-*/
|
||||
/***** Non-backup SRAM1 dedicated to M0+ code *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x2000C000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
|
||||
/***** Backup SRAM2 dedicated to M0+ data *****/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20004000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@ -0,0 +1,34 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20008000;
|
||||
/*-Memory Regions-*/
|
||||
/***** Non-backup SRAM1 dedicated to M4 code *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20008000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x2000BFFF;
|
||||
/***** Backup SRAM2 dedicated to M4 data *****/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@ -0,0 +1,40 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08020000;
|
||||
|
||||
/*-Memory Regions-*/
|
||||
/***** FLASH part dedicated to M0+ *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08020000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
|
||||
/***** SRAM1 dedicated to M0+ *****/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20004000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
||||
/***** SRAM2 dedicated to M0+ *****/
|
||||
define symbol __ICFEDIT_region_RAM2_start__ = 0x2000C000;
|
||||
define symbol __ICFEDIT_region_RAM2_end__ = 0x2000FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
place in RAM2_region { };
|
||||
@ -0,0 +1,40 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
|
||||
/*-Memory Regions-*/
|
||||
/***** FLASH part dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
|
||||
/***** Non-backup SRAM1 dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
|
||||
/***** Backup SRAM2 dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_RAM2_start__ = 0x20008000;
|
||||
define symbol __ICFEDIT_region_RAM2_end__ = 0x2000BFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
place in RAM2_region { };
|
||||
@ -0,0 +1,35 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x2000C000;
|
||||
|
||||
/*-Memory Regions-*/
|
||||
/***** Non-backup SRAM1 dedicated to M0+ code *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x2000C000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
|
||||
/***** Backup SRAM2 dedicated to M0+ data *****/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20004000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@ -0,0 +1,35 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20008000;
|
||||
|
||||
/*-Memory Regions-*/
|
||||
/***** Non-backup SRAM1 dedicated to M4 code *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20008000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x2000BFFF;
|
||||
/***** Backup SRAM2 dedicated to M4 data *****/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@ -0,0 +1,40 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
|
||||
/*-Memory Regions-*/
|
||||
/***** FLASH *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
|
||||
/***** Non-backup SRAM1 *****/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
||||
/***** Backup SRAM2 *****/
|
||||
define symbol __ICFEDIT_region_RAM2_start__ = 0x20008000;
|
||||
define symbol __ICFEDIT_region_RAM2_end__ = 0x2000FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
place in RAM2_region { };
|
||||
@ -0,0 +1,35 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
|
||||
/*-Memory Regions-*/
|
||||
/***** Non-backup SRAM1 dedicated to code *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x20007FFF;
|
||||
/***** Backup SRAM2 dedicated to data *****/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20008000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@ -0,0 +1,40 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
|
||||
/*-Memory Regions-*/
|
||||
/***** FLASH *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
|
||||
/***** Non-backup SRAM1 *****/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
||||
/***** Backup SRAM2 *****/
|
||||
define symbol __ICFEDIT_region_RAM2_start__ = 0x20008000;
|
||||
define symbol __ICFEDIT_region_RAM2_end__ = 0x2000FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
place in RAM2_region { };
|
||||
@ -0,0 +1,35 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
|
||||
/*-Memory Regions-*/
|
||||
/***** Non-backup SRAM1 dedicated to code *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x20007FFF;
|
||||
/***** Backup SRAM2 dedicated to data *****/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20008000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@ -0,0 +1,315 @@
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32wl54xx_cm0plus.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : MO+ core vector table of the STM32WLxxxx devices for the
|
||||
;* IAR (EWARM) toolchain.
|
||||
;*
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M0+ processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2020-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;
|
||||
;********************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD TZIC_ILA_IRQHandler ; TZIC ILA Interrupt
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
||||
DCD RTC_LSECSS_IRQHandler ; RTC Wakeup, Tamper, TimeStamp, RTC Alarms (A & B) and RTC SSRU Interrupts and LSECSS Interrupts
|
||||
DCD RCC_FLASH_C1SEV_IRQHandler ; RCC and FLASH and CPU1 M4 SEV Interrupt
|
||||
DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupt
|
||||
DCD EXTI3_2_IRQHandler ; EXTI Line 3:2 Interrupt
|
||||
DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupt
|
||||
DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupt
|
||||
DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupt
|
||||
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4,5,6,7 Interrupt
|
||||
DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
|
||||
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
|
||||
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
|
||||
|
||||
DCD TIM1_IRQHandler ; TIM1 Global Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
||||
DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupt
|
||||
DCD HSEM_IRQHandler ; Semaphore Interrupt
|
||||
DCD RNG_IRQHandler ; RNG Interrupt
|
||||
DCD AES_PKA_IRQHandler ; AES and PKA Interrupt
|
||||
DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
|
||||
DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
|
||||
DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK TZIC_ILA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TZIC_ILA_IRQHandler
|
||||
B TZIC_ILA_IRQHandler
|
||||
|
||||
PUBWEAK PVD_PVM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_PVM_IRQHandler
|
||||
B PVD_PVM_IRQHandler
|
||||
|
||||
PUBWEAK RTC_LSECSS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_LSECSS_IRQHandler
|
||||
B RTC_LSECSS_IRQHandler
|
||||
|
||||
PUBWEAK RCC_FLASH_C1SEV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_FLASH_C1SEV_IRQHandler
|
||||
B RCC_FLASH_C1SEV_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_0_IRQHandler
|
||||
B EXTI1_0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_2_IRQHandler
|
||||
B EXTI3_2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_4_IRQHandler
|
||||
B EXTI15_4_IRQHandler
|
||||
|
||||
PUBWEAK ADC_COMP_DAC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC_COMP_DAC_IRQHandler
|
||||
B ADC_COMP_DAC_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_2_3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_2_3_IRQHandler
|
||||
B DMA1_Channel1_2_3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_5_6_7_IRQHandler
|
||||
B DMA1_Channel4_5_6_7_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_DMAMUX1_OVR_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_DMAMUX1_OVR_IRQHandler
|
||||
B DMA2_DMAMUX1_OVR_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM3_IRQHandler
|
||||
B LPTIM3_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_IRQHandler
|
||||
B TIM1_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK TIM16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM16_IRQHandler
|
||||
B TIM16_IRQHandler
|
||||
|
||||
PUBWEAK TIM17_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM17_IRQHandler
|
||||
B TIM17_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C2_RX_C2_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C2_RX_C2_TX_IRQHandler
|
||||
B IPCC_C2_RX_C2_TX_IRQHandler
|
||||
|
||||
PUBWEAK HSEM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HSEM_IRQHandler
|
||||
B HSEM_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK AES_PKA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES_PKA_IRQHandler
|
||||
B AES_PKA_IRQHandler
|
||||
|
||||
PUBWEAK LCD_802_1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LCD_802_1_IRQHandler
|
||||
B LCD_802_1_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_IRQHandler
|
||||
B I2C1_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_IRQHandler
|
||||
B I2C2_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_IRQHandler
|
||||
B I2C3_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
PUBWEAK SUBGHZSPI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SUBGHZSPI_IRQHandler
|
||||
B SUBGHZSPI_IRQHandler
|
||||
|
||||
PUBWEAK SUBGHZ_Radio_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SUBGHZ_Radio_IRQHandler
|
||||
B SUBGHZ_Radio_IRQHandler
|
||||
|
||||
END
|
||||
@ -0,0 +1,508 @@
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32wl54xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : M4 core vector table of the STM32WLxxxx devices for the
|
||||
;* IAR (EWARM) toolchain.
|
||||
;*
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2020-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;
|
||||
;********************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
||||
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC_IRQHandler ; ADC Interrupt
|
||||
DCD DAC_IRQHandler ; DAC Interrupt
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
|
||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
||||
DCD AES_IRQHandler ; AES Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_PVM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_PVM_IRQHandler
|
||||
B PVD_PVM_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK DAC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DAC_IRQHandler
|
||||
B DAC_IRQHandler
|
||||
|
||||
PUBWEAK C2SEV_PWR_C2H_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
B C2SEV_PWR_C2H_IRQHandler
|
||||
|
||||
PUBWEAK COMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
COMP_IRQHandler
|
||||
B COMP_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_5_IRQHandler
|
||||
B EXTI9_5_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_BRK_IRQHandler
|
||||
B TIM1_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_UP_IRQHandler
|
||||
B TIM1_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
B TIM1_TRG_COM_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK TIM16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM16_IRQHandler
|
||||
B TIM16_IRQHandler
|
||||
|
||||
PUBWEAK TIM17_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM17_IRQHandler
|
||||
B TIM17_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_EV_IRQHandler
|
||||
B I2C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_ER_IRQHandler
|
||||
B I2C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM3_IRQHandler
|
||||
B LPTIM3_IRQHandler
|
||||
|
||||
PUBWEAK SUBGHZSPI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SUBGHZSPI_IRQHandler
|
||||
B SUBGHZSPI_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_RX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_RX_IRQHandler
|
||||
B IPCC_C1_RX_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_TX_IRQHandler
|
||||
B IPCC_C1_TX_IRQHandler
|
||||
|
||||
PUBWEAK HSEM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HSEM_IRQHandler
|
||||
B HSEM_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_EV_IRQHandler
|
||||
B I2C3_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_ER_IRQHandler
|
||||
B I2C3_ER_IRQHandler
|
||||
|
||||
PUBWEAK SUBGHZ_Radio_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SUBGHZ_Radio_IRQHandler
|
||||
B SUBGHZ_Radio_IRQHandler
|
||||
|
||||
PUBWEAK AES_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES_IRQHandler
|
||||
B AES_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK PKA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PKA_IRQHandler
|
||||
B PKA_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel1_IRQHandler
|
||||
B DMA2_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel2_IRQHandler
|
||||
B DMA2_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel3_IRQHandler
|
||||
B DMA2_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel4_IRQHandler
|
||||
B DMA2_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel5_IRQHandler
|
||||
B DMA2_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel6_IRQHandler
|
||||
B DMA2_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel7_IRQHandler
|
||||
B DMA2_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK DMAMUX1_OVR_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
B DMAMUX1_OVR_IRQHandler
|
||||
|
||||
END
|
||||
@ -0,0 +1,315 @@
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32wl55xx_cm0plus.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : MO+ core vector table of the STM32WLxxxx devices for the
|
||||
;* IAR (EWARM) toolchain.
|
||||
;*
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M0+ processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2020-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;
|
||||
;********************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD TZIC_ILA_IRQHandler ; TZIC ILA Interrupt
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
||||
DCD RTC_LSECSS_IRQHandler ; RTC Wakeup, Tamper, TimeStamp, RTC Alarms (A & B) and RTC SSRU Interrupts and LSECSS Interrupts
|
||||
DCD RCC_FLASH_C1SEV_IRQHandler ; RCC and FLASH and CPU1 M4 SEV Interrupt
|
||||
DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupt
|
||||
DCD EXTI3_2_IRQHandler ; EXTI Line 3:2 Interrupt
|
||||
DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupt
|
||||
DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupt
|
||||
DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupt
|
||||
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4,5,6,7 Interrupt
|
||||
DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
|
||||
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
|
||||
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
|
||||
|
||||
DCD TIM1_IRQHandler ; TIM1 Global Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
||||
DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupt
|
||||
DCD HSEM_IRQHandler ; Semaphore Interrupt
|
||||
DCD RNG_IRQHandler ; RNG Interrupt
|
||||
DCD AES_PKA_IRQHandler ; AES and PKA Interrupt
|
||||
DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
|
||||
DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
|
||||
DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK TZIC_ILA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TZIC_ILA_IRQHandler
|
||||
B TZIC_ILA_IRQHandler
|
||||
|
||||
PUBWEAK PVD_PVM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_PVM_IRQHandler
|
||||
B PVD_PVM_IRQHandler
|
||||
|
||||
PUBWEAK RTC_LSECSS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_LSECSS_IRQHandler
|
||||
B RTC_LSECSS_IRQHandler
|
||||
|
||||
PUBWEAK RCC_FLASH_C1SEV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_FLASH_C1SEV_IRQHandler
|
||||
B RCC_FLASH_C1SEV_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_0_IRQHandler
|
||||
B EXTI1_0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_2_IRQHandler
|
||||
B EXTI3_2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_4_IRQHandler
|
||||
B EXTI15_4_IRQHandler
|
||||
|
||||
PUBWEAK ADC_COMP_DAC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC_COMP_DAC_IRQHandler
|
||||
B ADC_COMP_DAC_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_2_3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_2_3_IRQHandler
|
||||
B DMA1_Channel1_2_3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_5_6_7_IRQHandler
|
||||
B DMA1_Channel4_5_6_7_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_DMAMUX1_OVR_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_DMAMUX1_OVR_IRQHandler
|
||||
B DMA2_DMAMUX1_OVR_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM3_IRQHandler
|
||||
B LPTIM3_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_IRQHandler
|
||||
B TIM1_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK TIM16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM16_IRQHandler
|
||||
B TIM16_IRQHandler
|
||||
|
||||
PUBWEAK TIM17_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM17_IRQHandler
|
||||
B TIM17_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C2_RX_C2_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C2_RX_C2_TX_IRQHandler
|
||||
B IPCC_C2_RX_C2_TX_IRQHandler
|
||||
|
||||
PUBWEAK HSEM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HSEM_IRQHandler
|
||||
B HSEM_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK AES_PKA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES_PKA_IRQHandler
|
||||
B AES_PKA_IRQHandler
|
||||
|
||||
PUBWEAK LCD_802_1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LCD_802_1_IRQHandler
|
||||
B LCD_802_1_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_IRQHandler
|
||||
B I2C1_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_IRQHandler
|
||||
B I2C2_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_IRQHandler
|
||||
B I2C3_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
PUBWEAK SUBGHZSPI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SUBGHZSPI_IRQHandler
|
||||
B SUBGHZSPI_IRQHandler
|
||||
|
||||
PUBWEAK SUBGHZ_Radio_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SUBGHZ_Radio_IRQHandler
|
||||
B SUBGHZ_Radio_IRQHandler
|
||||
|
||||
END
|
||||
@ -0,0 +1,508 @@
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32wl55xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : M4 core vector table of the STM32WLxxxx devices for the
|
||||
;* IAR (EWARM) toolchain.
|
||||
;*
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2020-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;
|
||||
;********************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
||||
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC_IRQHandler ; ADC Interrupt
|
||||
DCD DAC_IRQHandler ; DAC Interrupt
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
|
||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
||||
DCD AES_IRQHandler ; AES Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_PVM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_PVM_IRQHandler
|
||||
B PVD_PVM_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK DAC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DAC_IRQHandler
|
||||
B DAC_IRQHandler
|
||||
|
||||
PUBWEAK C2SEV_PWR_C2H_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
B C2SEV_PWR_C2H_IRQHandler
|
||||
|
||||
PUBWEAK COMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
COMP_IRQHandler
|
||||
B COMP_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_5_IRQHandler
|
||||
B EXTI9_5_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_BRK_IRQHandler
|
||||
B TIM1_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_UP_IRQHandler
|
||||
B TIM1_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
B TIM1_TRG_COM_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK TIM16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM16_IRQHandler
|
||||
B TIM16_IRQHandler
|
||||
|
||||
PUBWEAK TIM17_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM17_IRQHandler
|
||||
B TIM17_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_EV_IRQHandler
|
||||
B I2C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_ER_IRQHandler
|
||||
B I2C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM3_IRQHandler
|
||||
B LPTIM3_IRQHandler
|
||||
|
||||
PUBWEAK SUBGHZSPI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SUBGHZSPI_IRQHandler
|
||||
B SUBGHZSPI_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_RX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_RX_IRQHandler
|
||||
B IPCC_C1_RX_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_TX_IRQHandler
|
||||
B IPCC_C1_TX_IRQHandler
|
||||
|
||||
PUBWEAK HSEM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HSEM_IRQHandler
|
||||
B HSEM_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_EV_IRQHandler
|
||||
B I2C3_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_ER_IRQHandler
|
||||
B I2C3_ER_IRQHandler
|
||||
|
||||
PUBWEAK SUBGHZ_Radio_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SUBGHZ_Radio_IRQHandler
|
||||
B SUBGHZ_Radio_IRQHandler
|
||||
|
||||
PUBWEAK AES_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES_IRQHandler
|
||||
B AES_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK PKA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PKA_IRQHandler
|
||||
B PKA_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel1_IRQHandler
|
||||
B DMA2_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel2_IRQHandler
|
||||
B DMA2_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel3_IRQHandler
|
||||
B DMA2_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel4_IRQHandler
|
||||
B DMA2_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel5_IRQHandler
|
||||
B DMA2_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel6_IRQHandler
|
||||
B DMA2_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel7_IRQHandler
|
||||
B DMA2_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK DMAMUX1_OVR_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
B DMAMUX1_OVR_IRQHandler
|
||||
|
||||
END
|
||||
@ -0,0 +1,493 @@
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32wle4xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : M4 core vector table of the STM32WLxxxx devices for the
|
||||
;* IAR (EWARM) toolchain.
|
||||
;*
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2020-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;
|
||||
;********************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
||||
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC_IRQHandler ; ADC Interrupt
|
||||
DCD DAC_IRQHandler ; DAC Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
|
||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
||||
DCD AES_IRQHandler ; AES Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_PVM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_PVM_IRQHandler
|
||||
B PVD_PVM_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK DAC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DAC_IRQHandler
|
||||
B DAC_IRQHandler
|
||||
|
||||
PUBWEAK COMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
COMP_IRQHandler
|
||||
B COMP_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_5_IRQHandler
|
||||
B EXTI9_5_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_BRK_IRQHandler
|
||||
B TIM1_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_UP_IRQHandler
|
||||
B TIM1_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
B TIM1_TRG_COM_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK TIM16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM16_IRQHandler
|
||||
B TIM16_IRQHandler
|
||||
|
||||
PUBWEAK TIM17_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM17_IRQHandler
|
||||
B TIM17_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_EV_IRQHandler
|
||||
B I2C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_ER_IRQHandler
|
||||
B I2C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM3_IRQHandler
|
||||
B LPTIM3_IRQHandler
|
||||
|
||||
PUBWEAK SUBGHZSPI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SUBGHZSPI_IRQHandler
|
||||
B SUBGHZSPI_IRQHandler
|
||||
|
||||
PUBWEAK HSEM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HSEM_IRQHandler
|
||||
B HSEM_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_EV_IRQHandler
|
||||
B I2C3_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_ER_IRQHandler
|
||||
B I2C3_ER_IRQHandler
|
||||
|
||||
PUBWEAK SUBGHZ_Radio_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SUBGHZ_Radio_IRQHandler
|
||||
B SUBGHZ_Radio_IRQHandler
|
||||
|
||||
PUBWEAK AES_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES_IRQHandler
|
||||
B AES_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK PKA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PKA_IRQHandler
|
||||
B PKA_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel1_IRQHandler
|
||||
B DMA2_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel2_IRQHandler
|
||||
B DMA2_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel3_IRQHandler
|
||||
B DMA2_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel4_IRQHandler
|
||||
B DMA2_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel5_IRQHandler
|
||||
B DMA2_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel6_IRQHandler
|
||||
B DMA2_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel7_IRQHandler
|
||||
B DMA2_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK DMAMUX1_OVR_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
B DMAMUX1_OVR_IRQHandler
|
||||
|
||||
END
|
||||
@ -0,0 +1,493 @@
|
||||
;********************************************************************************
|
||||
;* File Name : startup_stm32wle5xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : M4 core vector table of the STM32WLxxxx devices for the
|
||||
;* IAR (EWARM) toolchain.
|
||||
;*
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2020-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;
|
||||
;********************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
||||
DCD TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC_IRQHandler ; ADC Interrupt
|
||||
DCD DAC_IRQHandler ; DAC Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD TIM16_IRQHandler ; TIM16 Global Interrupt
|
||||
DCD TIM17_IRQHandler ; TIM17 Global Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event Interrupt
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD USART2_IRQHandler ; USART2 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Global Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Global Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines [15:10] Interrupt
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD LPTIM3_IRQHandler ; LPTIM3 Global Interrupt
|
||||
DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
||||
DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
|
||||
DCD AES_IRQHandler ; AES Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_PVM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_PVM_IRQHandler
|
||||
B PVD_PVM_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
B TAMP_STAMP_LSECSS_SSRU_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK DAC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DAC_IRQHandler
|
||||
B DAC_IRQHandler
|
||||
|
||||
PUBWEAK COMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
COMP_IRQHandler
|
||||
B COMP_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_5_IRQHandler
|
||||
B EXTI9_5_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_BRK_IRQHandler
|
||||
B TIM1_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_UP_IRQHandler
|
||||
B TIM1_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
B TIM1_TRG_COM_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK TIM16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM16_IRQHandler
|
||||
B TIM16_IRQHandler
|
||||
|
||||
PUBWEAK TIM17_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM17_IRQHandler
|
||||
B TIM17_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_EV_IRQHandler
|
||||
B I2C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_ER_IRQHandler
|
||||
B I2C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM3_IRQHandler
|
||||
B LPTIM3_IRQHandler
|
||||
|
||||
PUBWEAK SUBGHZSPI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SUBGHZSPI_IRQHandler
|
||||
B SUBGHZSPI_IRQHandler
|
||||
|
||||
PUBWEAK HSEM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HSEM_IRQHandler
|
||||
B HSEM_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_EV_IRQHandler
|
||||
B I2C3_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_ER_IRQHandler
|
||||
B I2C3_ER_IRQHandler
|
||||
|
||||
PUBWEAK SUBGHZ_Radio_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SUBGHZ_Radio_IRQHandler
|
||||
B SUBGHZ_Radio_IRQHandler
|
||||
|
||||
PUBWEAK AES_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES_IRQHandler
|
||||
B AES_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK PKA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PKA_IRQHandler
|
||||
B PKA_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel1_IRQHandler
|
||||
B DMA2_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel2_IRQHandler
|
||||
B DMA2_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel3_IRQHandler
|
||||
B DMA2_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel4_IRQHandler
|
||||
B DMA2_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel5_IRQHandler
|
||||
B DMA2_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel6_IRQHandler
|
||||
B DMA2_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel7_IRQHandler
|
||||
B DMA2_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK DMAMUX1_OVR_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
B DMAMUX1_OVR_IRQHandler
|
||||
|
||||
END
|
||||
@ -0,0 +1,357 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32wlxx.c
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex Device Peripheral Access Layer System Source File
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2020-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32wlxx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* After each device reset the MSI (4 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32wlxx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
*-----------------------------------------------------------------------------
|
||||
* System Clock source | MSI
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(Hz) | 4000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* HCLK(Hz) | 4000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_M | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_N | 8
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_P | 7
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_Q | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_R | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLSAI1_P | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLSAI1_Q | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLSAI1_R | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* Require 48MHz for USB OTG FS, | Disabled
|
||||
* SDIO and RNG clock |
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32WLxx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32WLxx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32wlxx.h"
|
||||
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE (32000000UL) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (MSI_VALUE)
|
||||
#define MSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* MSI_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
|
||||
#endif /* LSI_VALUE */
|
||||
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WLxx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WLxx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Note: Following vector table addresses must be defined in line with linker
|
||||
configuration. */
|
||||
/*!< Uncomment the following line if you need to relocate CPU1 CM4 and/or CPU2
|
||||
CM0+ vector table anywhere in Sram or Flash. Else vector table will be kept
|
||||
at address 0x00 which correspond to automatic remap of boot address selected */
|
||||
/* #define USER_VECT_TAB_ADDRESS */
|
||||
#if defined(USER_VECT_TAB_ADDRESS)
|
||||
#ifdef CORE_CM0PLUS
|
||||
/*!< Uncomment this line for user vector table remap in Sram else user remap
|
||||
will be done in Flash. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS SRAM2_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x100. */
|
||||
#define VECT_TAB_OFFSET 0x00008000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x100. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x100. */
|
||||
#define VECT_TAB_OFFSET 0x00020000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x100. */
|
||||
#endif
|
||||
#else /* CORE_CM4 */
|
||||
/*!< Uncomment this line for user vector table remap in Sram else user remap
|
||||
will be done in Flash. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WLxx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WLxx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* The SystemCoreClock variable is updated in three ways:
|
||||
1) from within HAL_Init()
|
||||
2) by calling CMSIS function SystemCoreClockUpdate()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
*/
|
||||
uint32_t SystemCoreClock = 4000000UL; /*CPU1: M4 on MSI clock after startup (4MHz)*/
|
||||
|
||||
const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
|
||||
|
||||
const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
|
||||
|
||||
const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
|
||||
4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WLxx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WLxx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
#if defined(USER_VECT_TAB_ADDRESS)
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
|
||||
#endif
|
||||
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL))); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) MSI_VALUE is a constant defined in stm32wlxx_hal.h file (default value
|
||||
* 4 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSI_VALUE is a constant defined in stm32wlxx_hal_conf.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (***) HSE_VALUE is a constant defined in stm32wlxx_hal_conf.h file (default value
|
||||
* 32 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
|
||||
|
||||
/* Get MSI Range frequency--------------------------------------------------*/
|
||||
|
||||
/* Get MSI Range frequency--------------------------------------------------*/
|
||||
if((RCC->CR & RCC_CR_MSIRGSEL) == 0U)
|
||||
{ /* MSISRANGE from RCC_CSR applies */
|
||||
msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
|
||||
}
|
||||
else
|
||||
{ /* MSIRANGE from RCC_CR applies */
|
||||
msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
|
||||
}
|
||||
/*MSI frequency range in HZ*/
|
||||
msirange = MSIRangeTable[msirange];
|
||||
|
||||
|
||||
/*SystemCoreClock=HAL_RCC_GetSysClockFreq();*/
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
switch (RCC->CFGR & RCC_CFGR_SWS)
|
||||
{
|
||||
case 0x00: /* MSI used as system clock source */
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
|
||||
case 0x04: /* HSI used as system clock source */
|
||||
/* HSI used as system clock source */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
|
||||
case 0x08: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case 0x0C: /* PLL used as system clock source */
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
|
||||
SYSCLK = PLL_VCO / PLLR
|
||||
*/
|
||||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
|
||||
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
|
||||
|
||||
switch (pllsource)
|
||||
{
|
||||
case 0x02: /* HSI used as PLL clock source */
|
||||
pllvco = (HSI_VALUE / pllm);
|
||||
break;
|
||||
|
||||
case 0x03: /* HSE used as PLL clock source */
|
||||
pllvco = (HSE_VALUE / pllm);
|
||||
break;
|
||||
|
||||
default: /* MSI used as PLL clock source */
|
||||
pllvco = (msirange / pllm);
|
||||
break;
|
||||
}
|
||||
|
||||
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
||||
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
|
||||
|
||||
SystemCoreClock = pllvco/pllr;
|
||||
break;
|
||||
|
||||
default:
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Compute HCLK clock frequency --------------------------------------------*/
|
||||
#if defined(DUAL_CORE) && defined(CORE_CM0PLUS)
|
||||
/* Get HCLK2 prescaler */
|
||||
tmp = AHBPrescTable[((RCC->EXTCFGR & RCC_EXTCFGR_C2HPRE) >> RCC_EXTCFGR_C2HPRE_Pos)];
|
||||
#else
|
||||
/* Get HCLK1 prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
|
||||
#endif
|
||||
|
||||
/* Core clock frequency */
|
||||
SystemCoreClock = SystemCoreClock / tmp;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
Reference in New Issue
Block a user