crosstyan/zephyr_llcc68_driver
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feat(llcc68): honor directional TX settings

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Apply the SX126x IQ config register fix after each LoRa packet parameter update so standard and inverted IQ changes take effect.

Reapply TX power settings in LoRa and GFSK async flush paths so a TX profile can differ from the RX/init profile.
This commit is contained in:
crosstyan
2026-05-29 16:55:29 +08:00
parent d4709da971
commit 4fb41a3211
1 changed files with 11 additions and 1 deletions
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src/llcc68.cpp
+11 -1
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@@ -879,7 +879,9 @@ LLCC68::set_packet_params(uint16_t preamble_length, uint8_t payload_length,
crc_type,
iq_type,
};
return write_stream(RADIOLIB_SX126X_CMD_SET_PACKET_PARAMS, data);
auto r = write_stream(RADIOLIB_SX126X_CMD_SET_PACKET_PARAMS, data);
APP_RADIO_RETURN_ERR(r);
return fix_inverted_iq(iq_type);
}
expected<unit, error_code>
@@ -1307,6 +1309,10 @@ LLCC68::hal_async_flush(lora_parameters_t params) {
params.packet_params.hdr_type,
params.packet_params.iq_type),
"tx::set_packet_params");
auto chip_type_ = hal_get_chip_type();
APP_RADIO_RETURN_ERR_CTX(chip_type_, "tx::get_chip_type");
APP_RADIO_RETURN_ERR_CTX(hal_set_output_power(*chip_type_, params.tx_params),
"tx::hal_set_output_power");
APP_RADIO_RETURN_ERR_CTX(set_buffer_base_address(),
"tx::set_buffer_base_address");
APP_RADIO_RETURN_ERR_CTX(flush_tx_buffer(), "tx::flush_tx_buffer");
@@ -1360,6 +1366,10 @@ LLCC68::hal_gfsk_async_flush(gfsk_parameters_t params) {
packet_params.payload_length = static_cast<uint8_t>(data().tx_xfer_size);
APP_RADIO_RETURN_ERR_CTX(set_gfsk_packet_params(packet_params),
"gfsk_tx::set_packet_params");
auto chip_type_ = hal_get_chip_type();
APP_RADIO_RETURN_ERR_CTX(chip_type_, "gfsk_tx::get_chip_type");
APP_RADIO_RETURN_ERR_CTX(hal_set_output_power(*chip_type_, params.tx_params),
"gfsk_tx::hal_set_output_power");
APP_RADIO_RETURN_ERR_CTX(set_buffer_base_address(),
"gfsk_tx::set_buffer_base_address");
APP_RADIO_RETURN_ERR_CTX(flush_tx_buffer(), "gfsk_tx::flush_tx_buffer");