crosstyan 4fb41a3211 feat(llcc68): honor directional TX settings
Apply the SX126x IQ config register fix after each LoRa packet parameter update so standard and inverted IQ changes take effect.

Reapply TX power settings in LoRa and GFSK async flush paths so a TX profile can differ from the RX/init profile.
2026-05-29 19:40:56 +08:00
2026-05-19 10:48:52 +08:00
2026-05-19 10:48:52 +08:00
2026-05-19 10:30:34 +08:00
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